In association with a higher-speed operation of a semiconductor device, a high-speed signal transmission is carried out between various information processing apparatuses using the semiconductor devices. In the transmission, reflection of a signal occurs in a portion in which impedance is discontinuous. This signal reflection causes a problem in association with the advancement of the high-speed signal transmission. The impedance of a transmission line has a fixed value. On the contrary, the impedance of an output buffer varies depending on various situations such as a process, a temperature and a voltage. Accordingly, unless the impedance of the output buffer is properly adjusted to the impedance of the transmission line, it is impossible to carry out the high-speed signal transmission.
For this reason, an impedance matching is proposed in which an impedance adjustment output buffer is connected to an external clamp circuit that is set to be matched to the impedance of the transmission line, as described in Japanese Patent Application Publication (JP-P2005-229177A).
FIG. 1 is a circuit diagram showing the configuration of an impedance adjusting circuit in a related art. An impedance adjusting output buffer 103 is arranged in an LSI 102 as a semiconductor device accommodated in an LSI (Large Scale Integration) case 101 or PWB (Printed Wiring Board) in an impedance adjusting circuit 100. A variable resistor 104 is built in the impedance adjusting output buffer 103 and is attained through on/off operations of a plurality of transistors (not shown). A control circuit 105 controls the resistance of this variable resistor 104. The impedance adjusting output buffer 103 is connected to a clamp resistor 106 outside the LSI case 101. This clamp resistor 106 is a reference resistor, when the impedance is adjusted by the impedance adjusting output buffer 103. A line between the impedance adjusting output buffer 103 and the clamp resistor 106 has a predetermined parasitic resistance component 107. Outside the LSI case 101, in addition to the clamp resistor 106, there are arranged a first reference voltage generation resistor 111 and a second reference voltage generation resistor 112 which are connected in series between a power supply line 108 and the ground. A connection node between the first reference voltage generation resistor 111 and the second reference voltage generation resistor 112 is connected to a comparator 114 through a predetermined parasitic resistance component 113 and a voltage of the connection node is compared with a voltage at the output of the impedance adjusting output buffer 103. The control circuit 105 carries out the impedance matching by controlling the resistance of the variable resistor 104 based on the comparison result of the comparator 114.
Here, it is supposed that the parasitic resistance components 107 and 113 can be ignored. In this case, the control circuit 105 controls the resistance of the variable resistor 104 so that the voltage applied to a positive input terminal of the comparator 114 and the voltage applied to a negative input terminal thereof become equal. When the voltages applied to the these two input terminals of the comparator 114 become equal, the impedance matching on the side of the impedance adjusting output buffer 103 is assumed to be attained.
However, in the impedance adjusting circuit 100 in this related art, there is a line between the clamp resistor 106 outside the LSI case 101 and the LSI 102 in the LSI case 101. Since the connection node between the first reference voltage generation resistor 111 and the second reference voltage generation resistor 112 similarly exists outside the LSI case 101, a line exist between the connection node and the LSI 102. Since these lines have parasitic resistance components 107 and 113, the voltage differences are generated due to those portions. For this reason, at the two input terminals of the comparator 114, it is impossible to accurately compare a voltage resulting from the clamp resistor 106 and a voltage at the connection node between the first reference voltage generation resistor 111 and the second reference voltage generation resistor 112. As a result, an error is generated in the resistance of the variable resistor 104 controlled by the control circuit 105. Consequently, the compensation of the impedance adjusting output buffer 103 is imperfectly executed, and the impedance matching cannot be carried out in a sufficient precision.
Conventionally, a proposal is given in which a resistor having a resistance corresponding to the parasitic resistance component is added to the circuit to compensate the error. Consequently, it is possible to improve the precision of the impedance matching. However, the resistor to be added to outside is based on [E Series] serving as the standard number that a value between [1] and [10] is divided by a geometric series. For example, in the E12 series, the range is divided by 12, and in the E14 series, the range is divided by 24. Thus, when a small resistance such as the parasitic resistance is compensated outside the LSI case 101, any one of the resistance values in those series is selected and employed. Thus, it is impossible to sufficiently compensate the error.
The proposal shown in FIG. 1 is designed in such a manner that the resistance of the adjusting circuit is N (N is any integer) times the resistance of the circuit to be adjusted, and the error is reduced to 1/N, to reduce the compensation error. However, as mentioned above, since the improvement of the operation speed of the impedance adjusting circuit is remarkable, a higher precision of the impedance matching is required. Thus, it is difficult to adjust the impedance on the semiconductor device side in a sufficient precision by using the related art.